Advanced RISC-V 32-bit SoC - RV32IM core with 5 stage pipeline, L1(I/D) Cache, AXI4 Bus Arbiter, and upcoming 7-stage pipeline, IME (Zvvm) Matrix Extension
cpu fpga pipeline hardware ime cache rtl vivado systemverilog soc vlsi risc-v branch-prediction rv32im axi4 rvv kv260 matrix-extension zvvm
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Updated
Apr 19, 2026 - C