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Priority determination behavior for hviprio*

Status: Open.

#164 In riscv/riscv-aia;

· inochisa opened on Apr 19, 2026

Reserved values for vscause

Status: Open.

#162 In riscv/riscv-aia;

· chenwhJ opened on Apr 10, 2026

Priority number for external interrupts

Status: Open.

#161 In riscv/riscv-aia;

· pkennedyTT opened on Apr 8, 2026

pcie send intx to system, the APLIC change the intx to msi, this msi whether need to translate by IOMMU ?

Status: Open.

#160 In riscv/riscv-aia;

· 123wh123 opened on Mar 23, 2026

Confirmation of the conditions for wfi wake-up

Status: Open.

#159 In riscv/riscv-aia;

· ic-nerd opened on Mar 13, 2026

vs/vu access stopei raise illegal instruction exception or virtual instruction exception?

Status: Open.

#158 In riscv/riscv-aia;

· shengqilong opened on Mar 11, 2026

About updating mip.SEIP and resume from WFI

Status: Open.

#154 In riscv/riscv-aia;

· ningge666 opened on Jan 31, 2026

MSI transmission behavior when setipnum is triggered while enable bit is disabled for level-sensitive sources

Status: Open.

#153 In riscv/riscv-aia;

· xingpenghu opened on Jan 17, 2026

'iprio' (AIA) and ‘eipX/eieX'(IMSIC) indirect CSRs access control when relative bit in mstateen0 is clear

Status: Open.

#151 In riscv/riscv-aia;

· Steven-Li-Xiaogang opened on Dec 26, 2025

Interrupt filtering and virtual interrupts for supervisor level

Status: Open.

#150 In riscv/riscv-aia;

· KirillMillstone opened on Dec 16, 2025

When bit 9 of mvien is zero, when mvip is read with a CSR instruction, the value of the SEIP bit returned in the rd destination register is what？

Status: Open.

#147 In riscv/riscv-aia;

· ic-nerd opened on Nov 4, 2025

Why attempts from VS-mode to access sireg (really vsireg)(inaccessible register) raise a virtual instruction exception?

Status: Open.

#146 In riscv/riscv-aia;

· gamber27 opened on Oct 22, 2025