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30 Days of Verilog

A personal challenge to learn, build, and document digital design using Verilog.


⚙️ Overview

Welcome to 30 Days of Verilog — my hands-on journey through the world of digital design and Verilog HDL.
The goal is simple: build 30 digital circuits in 30 days, understand how they work, and share what I learn

I didn’t post daily updates here, while this repository serves as the complete technical record of the work.


🎯 Objectives

  • Master Verilog — Build a solid foundation in hardware description and logic design.
  • Explore Digital Circuits — Implement and simulate a wide range of classic designs.
  • Document the Journey — Record the process, challenges, and insights from each build.
  • Give Back — Share examples others can learn from or build upon.

🗂️ Repository Structure

Each day’s work is organized into a folder: Day 1 to Day 30, containing:

  • Verilog Code — The design files (.v) and testbenches.
  • README — A short explanation of the circuit, purpose, and logic.
  • Simulations — Waveforms and test outputs (if applicable).
  • Reflections — Notes, challenges faced, and lessons learned.

📘 Table of Contents


🤝 Connect

If you’re learning Verilog or digital design, I’d love to connect and exchange ideas:


🧩 Final Thoughts

This project is about more than code — it’s about consistency, curiosity, and craftsmanship.
Each circuit reflects a step toward mastering digital logic, one Verilog module at a time.

Happy Verilog Coding! 💻

About

This repository contains 30 digital designs from adders and counters to sequence detectors and controllers each with Verilog code, testbenches, simulations, and reflections. The goal is to build a strong foundation in hardware description, understand classic digital logic, and share the learning journey with others.

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