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Designing CMOS Layouts using Cadence Virtuoso
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Designing CMOS Layouts using Cadence Virtuoso

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  1. full-adder-cadence-project full-adder-cadence-project Public

    CMOS Full Adder design using Cadence Virtuoso including schematic design, simulation and layout verification (DRC, LVS REX).

  2. half-adder-cadence-project half-adder-cadence-project Public

    CMOS Half Adder design using Cadence Virtuoso including schematic design, simulation and layout verification (DRC, LVS REX).

  3. xnor-gate-cadence-project xnor-gate-cadence-project Public

    CMOS XnOR Gate design using Cadence Virtuoso including schematic design, simulation and layout verification (DRC, LVS REX).

  4. xor-gate-cadence-project xor-gate-cadence-project Public

    CMOS XOR Gate design using Cadence Virtuoso including schematic design, simulation and layout verification (DRC, LVS REX).

  5. nand-gate-cadence-project nand-gate-cadence-project Public

    CMOS NAND Gate design using Cadence Virtuoso including schematic design, simulation and layout verification (DRC, LVS REX).

  6. nor-gate-cadence-project nor-gate-cadence-project Public

    CMOS NOR Gate design using Cadence Virtuoso including schematic design, simulation, layout implementation and verification (DRC, LVS, REX).