Pinned Loading

1. FPGA-ACC-MAC FPGA-ACC-MAC Public

   4×4 7-bit matrix multiplication hardware accelerator using a systolic array, with a Python driver for the Basys 3 FPGA and a systolic array UVC using UVM.

   SystemVerilog 1 1

2. Uart-Protocol-RTL Uart-Protocol-RTL Public

   8bit - UART protocol

   SystemVerilog

3. 8bitpath-AES-AHB 8bitpath-AES-AHB Public

   Project for Soc Design, Follows a paper proposal for 8bitpath AES acclerator with AHB interface

   SystemVerilog

4. Convoloution_ACC Convoloution_ACC Public

   3 by 3 Kernel Convoloution Img processing accrelator for pynqZ2.

   VHDL