RegisterTransferLevel

This Repo contains Verilog Codes of RTLs via Xilinx Vivado

Name		Name	Last commit message	Last commit date
Latest commit History 28 Commits
2_4decoder		2_4decoder
8to3_PriorityEncoder		8to3_PriorityEncoder
BCD_to_7segment		BCD_to_7segment
Bidirectional_Shift_Register		Bidirectional_Shift_Register
Carry_LookAhead		Carry_LookAhead
Clock_Divider		Clock_Divider
Comparator		Comparator
D flip flop		D flip flop
Demux_8to1		Demux_8to1
Down Counter		Down Counter
Full_Adder		Full_Adder
Full_Subtractor		Full_Subtractor
Half_Adder		Half_Adder
Half_Subtractor		Half_Subtractor
Input_Majority		Input_Majority
JKFlip Flop		JKFlip Flop
MOD10_Counter		MOD10_Counter
MUX_8X1		MUX_8X1
Master_Slave_FF		Master_Slave_FF
N_bit_Parallel_Adder		N_bit_Parallel_Adder
Parallel In Parallel Out		Parallel In Parallel Out
SR FF		SR FF
Serial In Parallel Out		Serial In Parallel Out
Serial in serial out		Serial in serial out
T Flip Flop		T Flip Flop
UpCounter		UpCounter
Up_Down_Counter		Up_Down_Counter
srlatch		srlatch
.gitattributes		.gitattributes
README.md		README.md

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