Removed tests needing hardware performance counters during GitHub CI. Fixed warnings on using optionls without testing.

Author: jmuehlig

.github/workflows/build-and-test.yml

@@ -33,4 +33,4 @@ jobs:
         run: cmake --build build --target tests
 
       - name: Test
-        run: ./build/bin/tests ~[EventCounter] ~[Sampler] ~[HardwareInfo]
+        run: ./build/bin/tests ~[EventCounter] ~[Sampler] ~[HardwareInfo] ~[MultiThreadEventCounter] ~[MultiThreadSampler]

src/counter/counter.cpp

@@ -271,11 +271,12 @@ perf::Counter::create_perf_event_attribute(const bool is_disabled,
   /// have a sample type but are not truly sampling. We assume that true sampling is only requested when
   /// period/frequency and precision is set since both are needed for sampling but not for reading counter without
   /// stopping.
-  if (this->_config.period_or_frequency().has_value() && this->_config.precision().has_value()) {
+  if (const auto period_or_frequency = this->_config.period_or_frequency();
+      period_or_frequency.has_value() && this->_config.precision().has_value()) {
     attribute.sample_id_all = 1U;
 
     /// Set period of frequency, based on the PeriodOrFrequency variant.
-    std::visit(PeriodOrFrequencyVisitor{ attribute }, this->_config.period_or_frequency().value());
+    std::visit(PeriodOrFrequencyVisitor{ attribute }, period_or_frequency.value());
 
     /// Set sampled fields.
     attribute.branch_sample_type = sample_recording_values.branch_mask();

src/counter/event_provider.cpp

@@ -229,16 +229,20 @@ perf::AMDIbsEventProvider::add_fetch_events(CounterDefinition& counter_definitio
 {
   const auto& ibs_info = HardwareInfo::amd_ibs();
   if (const auto fetch_type = ibs_info.fetch_type(); ibs_info.is_supported() && fetch_type.has_value()) {
-    const auto rand_value = ibs_info.fetch_rand_bit().has_value() ? 1ULL << ibs_info.fetch_rand_bit().value() : 0ULL;
+    /// Setup random bit if requested.
+    auto rand_value = 0UL;
+    if (const auto rand_bit = ibs_info.fetch_rand_bit(); rand_bit.has_value()) {
+      rand_value = 1UL << rand_bit.value();
+    }
+
     /// Event that is triggered by cycles.
     counter_definition.add("ibs_fetch", "ibs_fetch", CounterConfig{ fetch_type.value(), rand_value });
 
     if (const auto l3_miss_only_bit = ibs_info.fetch_l3_miss_only_bit(); l3_miss_only_bit.has_value()) {
       /// Event that is triggered by cycles and applies the L3 miss filter.
-      counter_definition.add(
-        "ibs_fetch",
-        "ibs_fetch_l3missonly",
-        CounterConfig{ ibs_info.fetch_type().value(), rand_value | (1ULL << l3_miss_only_bit.value()) });
+      counter_definition.add("ibs_fetch",
+                             "ibs_fetch_l3missonly",
+                             CounterConfig{ fetch_type.value(), rand_value | (1ULL << l3_miss_only_bit.value()) });
     }
   }
 }