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Commit 7a52944

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author
cesare
committed
v2.2.7
- Add support for IAR tools and C startup code (irq vector) - Fix standard CLINT vectored mode (jmp instr) - Fix various trap & emulation bugs (E21 CLIC) - Add vector table mtvec.s (CLINT/CLIC) - Minor changes to zones' code to comply with standard CLINT vector - hexfive-conf @29253d, hexfive-kern @3d13f6
1 parent e42eee5 commit 7a52944

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26 files changed

+516
-245
lines changed

26 files changed

+516
-245
lines changed

‎.settings/language.settings.xml‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
55
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
66
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
7-
<provider class="org.eclipse.cdt.internal.build.crossgcc.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1517506878985792960" id="org.eclipse.cdt.build.crossgcc.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -march=rv32i -mabi=ilp32 -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
7+
<provider class="org.eclipse.cdt.internal.build.crossgcc.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1514948786892984960" id="org.eclipse.cdt.build.crossgcc.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -march=rv32i -mabi=ilp32 -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
88
<language-scope id="org.eclipse.cdt.core.gcc"/>
99
<language-scope id="org.eclipse.cdt.core.g++"/>
1010
</provider>
@@ -14,7 +14,7 @@
1414
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
1515
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
1616
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
17-
<provider class="org.eclipse.cdt.internal.build.crossgcc.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1512932981994239872" id="org.eclipse.cdt.build.crossgcc.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
17+
<provider class="org.eclipse.cdt.internal.build.crossgcc.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1510374889901431872" id="org.eclipse.cdt.build.crossgcc.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
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<language-scope id="org.eclipse.cdt.core.gcc"/>
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<language-scope id="org.eclipse.cdt.core.g++"/>
2020
</provider>
@@ -24,7 +24,7 @@
2424
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
2525
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
2626
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
27-
<provider class="org.eclipse.cdt.internal.build.crossgcc.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1517506878985792960" id="org.eclipse.cdt.build.crossgcc.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -march=rv32i -mabi=ilp32 -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true" store-entries-with-project="false">
27+
<provider class="org.eclipse.cdt.internal.build.crossgcc.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1514948786892984960" id="org.eclipse.cdt.build.crossgcc.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -march=rv32i -mabi=ilp32 -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true" store-entries-with-project="false">
2828
<language-scope id="org.eclipse.cdt.core.gcc"/>
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<language-scope id="org.eclipse.cdt.core.g++"/>
3030
</provider>
@@ -34,7 +34,7 @@
3434
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
3535
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
3636
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
37-
<provider class="org.eclipse.cdt.internal.build.crossgcc.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1517506878985792960" id="org.eclipse.cdt.build.crossgcc.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -march=rv32i -mabi=ilp32 -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true" store-entries-with-project="false">
37+
<provider class="org.eclipse.cdt.internal.build.crossgcc.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1514948786892984960" id="org.eclipse.cdt.build.crossgcc.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -march=rv32i -mabi=ilp32 -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true" store-entries-with-project="false">
3838
<language-scope id="org.eclipse.cdt.core.gcc"/>
3939
<language-scope id="org.eclipse.cdt.core.g++"/>
4040
</provider>
@@ -44,7 +44,7 @@
4444
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
4545
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
4646
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
47-
<provider class="org.eclipse.cdt.internal.build.crossgcc.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1517506878985792960" id="org.eclipse.cdt.build.crossgcc.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -march=rv32i -mabi=ilp32 -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true" store-entries-with-project="false">
47+
<provider class="org.eclipse.cdt.internal.build.crossgcc.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1514948786892984960" id="org.eclipse.cdt.build.crossgcc.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -march=rv32i -mabi=ilp32 -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true" store-entries-with-project="false">
4848
<language-scope id="org.eclipse.cdt.core.gcc"/>
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<language-scope id="org.eclipse.cdt.core.g++"/>
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</provider>

‎bsp/E21/multizone.cfg‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ Zone = 1
1111
clic = 159 # UART
1212
base = 0x40408000; size = 32K; rwx = rx # FLASH
1313
base = 0x80003000; size = 4K; rwx = rw # RAM
14-
base = 0x20000000; size = 0x100; rwx = rw # UART
14+
base = 0x20000000; size = 0x100; rwx = rw # UART
1515
base = 0x02800000; size =0x1000; rwx = r # CLIC (ro)
1616

1717
Zone = 2

‎bsp/E21/newlib/crt0.S‎

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Original file line numberDiff line numberDiff line change
@@ -7,6 +7,12 @@
77
_start:
88
.cfi_startproc
99
.cfi_undefined ra
10+
11+
/* setup trap vector - CLIC vectored mode */
12+
la a0, _mtvec
13+
csrw mtvec, a0
14+
csrs mtvec, 0b11
15+
1016
.option push
1117
.option norelax
1218
la gp, __global_pointer$
@@ -64,3 +70,5 @@ _init: ret
6470
.type _fini, @function
6571
_fini: ret
6672
.size _fini, .-_fini
73+
74+
.include "mtvec.s"

‎bsp/E21/newlib/mtvec.s‎

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,62 @@
1+
/* Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved */
2+
3+
.align 2
4+
5+
_mtvec:
6+
7+
irq0: .word trp_isr
8+
irq1: .word 1f
9+
irq2: .word 1f
10+
irq3: .word msi_isr
11+
irq4: .word 1f
12+
irq5: .word 1f
13+
irq6: .word 1f
14+
irq7: .word tmr_isr
15+
irq8: .word 1f
16+
irq9: .word 1f
17+
irq10: .word 1f
18+
irq11: .word 1f
19+
irq12: .word 1f
20+
irq13: .word 1f
21+
irq14: .word 1f
22+
irq15: .word 1f
23+
irq16: .word 1f
24+
irq17: .word 1f
25+
irq18: .word 1f
26+
irq19: .word dma_isr
27+
irq20: .word btn0_isr
28+
irq21: .word btn1_isr
29+
irq22: .word btn2_isr
30+
irq23: .word 1f
31+
irq24: .word 1f
32+
irq25: .word 1f
33+
irq26: .word 1f
34+
irq27: .word 1f
35+
irq28: .word 1f
36+
irq29: .word 1f
37+
irq30: .word 1f
38+
irq31: .word 1f
39+
40+
.macro FILL from, to
41+
.word 1f
42+
.if \to-\from
43+
FILL "(\from+1)",\to
44+
.endif
45+
.endm
46+
47+
FILL 32, 99
48+
FILL 100, 158
49+
50+
irq159: .word uart_isr
51+
52+
.weak trp_isr, msi_isr, tmr_isr, dma_isr, uart_isr, btn0_isr, btn1_isr, btn2_isr
53+
54+
trp_isr:
55+
msi_isr:
56+
tmr_isr:
57+
dma_isr:
58+
uart_isr:
59+
btn0_isr:
60+
btn1_isr:
61+
btn2_isr:
62+
1: j .

‎bsp/E21/newlib/newlib.mk‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@ all: $(TARGET)
66
ASM_SRCS += $(NEWLIB_DIR)/crt0.S
77
C_SRCS += $(NEWLIB_DIR)/newlib.c
88

9+
INCLUDES += -I$(NEWLIB_DIR)
910
INCLUDES += -I$(PLATFORM_DIR)
1011

1112
LDFLAGS += -T $(PLATFORM_DIR)/memory.lds

‎bsp/E21/platform.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -104,9 +104,9 @@
104104
#define BTN2 6
105105
#define BTN3 7
106106

107-
#define BTN0_IRQ 16+4
108-
#define BTN1_IRQ 16+5
109-
#define BTN2_IRQ 16+6
107+
#define BTN0_IRQ 20
108+
#define BTN1_IRQ 21
109+
#define BTN2_IRQ 22
110110

111111
// -----------------------------------------------------------------------------
112112
// LED0 (GPIO)
@@ -140,7 +140,7 @@
140140
#define _REG64(base, offset) (*(volatile uint64_t *)((base) + (offset)))
141141
#define _REG32(base, offset) (*(volatile uint32_t *)((base) + (offset)))
142142

143-
#define CLIC_REG(offset) _REG64(CLIC_BASE, offset)
143+
#define CLIC_REG(offset) _REG32(CLIC_BASE, offset)
144144
#define GPIO_REG(offset) _REG32(GPIO_BASE, offset)
145145
#define PWM_REG(offset) _REG32(PWM_BASE, offset)
146146
#define UART_REG(offset) _REG32(UART_BASE, offset)

‎bsp/E31/newlib/crt0.S‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,12 @@
77
_start:
88
.cfi_startproc
99
.cfi_undefined ra
10+
11+
/* setup trap vector */
12+
la a0, _mtvec
13+
csrw mtvec, a0
14+
csrs mtvec, 1
15+
1016
.option push
1117
.option norelax
1218
la gp, __global_pointer$
@@ -36,7 +42,6 @@ _start:
3642
bltu a0, a1, 1b
3743
2:
3844

39-
4045
/* Call global constructors */
4146
la a0, __libc_fini_array
4247
call atexit
@@ -65,3 +70,5 @@ _init: ret
6570
.type _fini, @function
6671
_fini: ret
6772
.size _fini, .-_fini
73+
74+
.include "mtvec.s"

‎bsp/E31/newlib/mtvec.s‎

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
1+
/* Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved */
2+
3+
.align 2
4+
5+
_mtvec:
6+
7+
.option push
8+
.option norvc
9+
10+
irq0: j trp_isr
11+
irq1: j .
12+
irq2: j .
13+
irq3: j msi_isr
14+
irq4: j .
15+
irq5: j .
16+
irq6: j .
17+
irq7: j tmr_isr
18+
irq8: j .
19+
irq9: j .
20+
irq10: j .
21+
irq11: j uart_isr
22+
irq12: j .
23+
irq13: j .
24+
irq14: j .
25+
irq15: j .
26+
irq16: j .
27+
irq17: j .
28+
irq18: j .
29+
irq19: j dma_isr
30+
irq20: j btn0_isr
31+
irq21: j btn1_isr
32+
irq22: j btn2_isr
33+
irq23: j .
34+
irq24: j .
35+
irq25: j .
36+
irq26: j .
37+
irq27: j .
38+
irq28: j .
39+
irq29: j .
40+
irq30: j .
41+
irq31: j .
42+
43+
.option pop
44+
45+
.weak trp_isr, msi_isr, tmr_isr, dma_isr, uart_isr, btn0_isr, btn1_isr, btn2_isr
46+
47+
trp_isr:
48+
msi_isr:
49+
tmr_isr:
50+
dma_isr:
51+
uart_isr:
52+
btn0_isr:
53+
btn1_isr:
54+
btn2_isr:
55+
j .

‎bsp/E31/newlib/newlib.mk‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@ all: $(TARGET)
66
ASM_SRCS += $(NEWLIB_DIR)/crt0.S
77
C_SRCS += $(NEWLIB_DIR)/newlib.c
88

9+
INCLUDES += -I$(NEWLIB_DIR)
910
INCLUDES += -I$(PLATFORM_DIR)
1011

1112
LDFLAGS += -T $(PLATFORM_DIR)/memory.lds

‎bsp/FE310/mtvec.s‎

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
1+
/* Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved */
2+
3+
.align 2
4+
5+
_mtvec:
6+
7+
.option push
8+
.option norvc
9+
10+
irq0: j trp_isr
11+
irq1: j .
12+
irq2: j .
13+
irq3: j msi_isr
14+
irq4: j .
15+
irq5: j .
16+
irq6: j .
17+
irq7: j tmr_isr
18+
irq8: j .
19+
irq9: j .
20+
irq10: j .
21+
irq11: j uart_isr
22+
irq12: j .
23+
irq13: j .
24+
irq14: j .
25+
irq15: j .
26+
irq16: j .
27+
irq17: j .
28+
irq18: j .
29+
irq19: j dma_isr
30+
irq20: j .
31+
irq21: j .
32+
irq22: j .
33+
irq23: j .
34+
irq24: j .
35+
irq25: j .
36+
irq26: j .
37+
irq27: j .
38+
irq28: j .
39+
irq29: j .
40+
irq30: j .
41+
irq31: j .
42+
43+
.option pop
44+
45+
.weak trp_isr, msi_isr, tmr_isr, dma_isr, uart_isr, btn0_isr, btn1_isr, btn2_isr
46+
47+
trp_isr:
48+
msi_isr:
49+
tmr_isr:
50+
dma_isr:
51+
uart_isr:
52+
btn0_isr:
53+
btn1_isr:
54+
btn2_isr:
55+
j .

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