Updated filename

Author: chmoore889

src/design/fake_combiner.vhd src/design/linear_buffer.vhdsrc/design/fake_combiner.vhd renamed to src/design/linear_buffer.vhd

@@ -3,7 +3,7 @@ use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 use work.time_multiplex.ALL;
 
-entity fake_combiner is
+entity linear_buffer is
     Generic (
         numChannels : integer
     );
@@ -17,9 +17,9 @@ entity fake_combiner is
            Dout : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
            DRdy : out STD_LOGIC := '0';
            EODout : out STD_LOGIC := '0');
-end fake_combiner;
+end linear_buffer;
 
-architecture Behavioral of fake_combiner is begin    
+architecture Behavioral of linear_buffer is begin    
     output_pipeline : process(clk) begin
         if rising_edge(clk) then
             if Reset = '1' then

src/design/linear_correlator.vhd

@@ -45,7 +45,7 @@ architecture Behavioral of linear_correlator is
                DoutRdy : out STD_LOGIC := '0');
     end component;
 
-    component fake_combiner is
+    component linear_buffer is
         Generic (
             numChannels : integer
         );
@@ -188,7 +188,7 @@ begin
 
             signal correlator_NDin, correlator_EODin : STD_LOGIC;
         begin
-            combine_A : fake_combiner
+            buff_A : linear_buffer
             generic map (
                 numChannels => numChannels
             )
@@ -205,7 +205,7 @@ begin
                 EODout => A_EODout
             );
 
-            combine_B : fake_combiner
+            buff_B : linear_buffer
             generic map (
                 numChannels => numChannels
             )

src/design/top.vhd

@@ -95,7 +95,7 @@ architecture Behavioral of top is
     end component;
 
     constant numChannels : integer := 1;
-    constant isMultiTau : boolean := true;
+    constant isMultiTau : boolean := false;
 
     signal DinCorr : STD_LOGIC_VECTOR (15 downto 0);
     signal ChaInSel : STD_LOGIC_VECTOR (channels_to_bits(numChannels) - 1 downto 0);

vivado_project.tcl

@@ -26,7 +26,7 @@ proc checkRequiredFiles { origin_dir} {
    "${origin_dir}/src/design/correlator.vhd" \
    "${origin_dir}/src/design/counter.vhd" \
    "${origin_dir}/src/design/dsp_multiply_and_accumulate.vhd" \
-   "${origin_dir}/src/design/fake_combiner.vhd" \
+   "${origin_dir}/src/design/linear_buffer.vhd" \
    "${origin_dir}/src/design/linear_correlator.vhd" \
    "${origin_dir}/src/design/mac_counter.vhd" \
    "${origin_dir}/src/design/multi_tau_correlator.vhd" \
@@ -196,7 +196,7 @@ set files [list \
  [file normalize "${origin_dir}/src/design/correlator.vhd"] \
  [file normalize "${origin_dir}/src/design/counter.vhd"] \
  [file normalize "${origin_dir}/src/design/dsp_multiply_and_accumulate.vhd"] \
- [file normalize "${origin_dir}/src/design/fake_combiner.vhd"] \
+ [file normalize "${origin_dir}/src/design/linear_buffer.vhd"] \
  [file normalize "${origin_dir}/src/design/linear_correlator.vhd"] \
  [file normalize "${origin_dir}/src/design/mac_counter.vhd"] \
  [file normalize "${origin_dir}/src/design/multi_tau_correlator.vhd"] \
@@ -261,7 +261,7 @@ set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "file_type" -value "VHDL" -objects $file_obj
 
-set file "$origin_dir/src/design/fake_combiner.vhd"
+set file "$origin_dir/src/design/linear_buffer.vhd"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "file_type" -value "VHDL" -objects $file_obj