Merge branch 'main' into feat/tda4vm_plat_support

Author: puranikvinit

scripts/arch/riscv/platform_defs_gen.c

@@ -14,6 +14,17 @@ void arch_platform_defs() {
 
     if (IRQC == AIA) {
         printf("#define PLAT_IMSIC_MAX_INTERRUPTS %ld\n", platform.arch.irqc.aia.imsic.num_msis);
+
+        /**
+         * This calculation follows the rules for the arrangement of memory regions for multiple
+         * interrupt files defined in section 3.6 of "The RISC-V Advanced Interrupt Architecture"
+         * version 1.0, with the smallest constant D as defined by the spec.
+         */
+        size_t num_addr_bits = 0;
+        while ((1UL << num_addr_bits) < (platform.arch.irqc.aia.imsic.num_guest_files + 1)) {
+            num_addr_bits += 1;
+        }
+        printf("#define PLAT_IMSIC_HART_SIZE (%ld)\n", ((1UL << (num_addr_bits)) * PAGE_SIZE));
     }
 
 }

src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h

@@ -71,6 +71,7 @@ SYSREG_GEN_ACCESSORS(clidr_el1, 1, c0, c0, 1)
 SYSREG_GEN_ACCESSORS(csselr_el1, 2, c0, c0, 0)
 SYSREG_GEN_ACCESSORS(ctr_el0, 0, c0, c0, 1)
 SYSREG_GEN_ACCESSORS(mpidr_el1, 0, c0, c0, 5)
+SYSREG_GEN_ACCESSORS(midr_el1, 0, c0, c0, 0)
 SYSREG_GEN_ACCESSORS(vmpidr_el2, 4, c0, c0, 5)
 SYSREG_GEN_ACCESSORS_64(cntvoff_el2, 4, c14)
 SYSREG_GEN_ACCESSORS(sctlr_el1, 0, c1, c0, 0)
@@ -117,6 +118,10 @@ SYSREG_GEN_ACCESSORS_64(icc_sgi1r_el1, 0, c12)
 SYSREG_GEN_ACCESSORS(vsctlr_el2, 4, c2, c0, 0)
 SYSREG_GEN_ACCESSORS(sctlr_el2, 4, c1, c0, 0)
 
+SYSREG_GEN_ACCESSORS(hactlr, 4, c1, c0, 1)
+SYSREG_GEN_ACCESSORS(imp_periphregionr, 0, c15, c0, 0)
+SYSREG_GEN_ACCESSORS(flashifregionr, 0, c15, c0, 1)
+
 #define SYSREG_GEN_GIC_LR(n, crn1, crn2, op2)           \
     SYSREG_GEN_ACCESSORS(ich_lr##n, 4, c12, crn1, op2)  \
     SYSREG_GEN_ACCESSORS(ich_lrc##n, 4, c12, crn2, op2) \

src/arch/armv8/aarch64/inc/arch/subarch/sysregs.h

@@ -69,6 +69,7 @@ SYSREG_GEN_ACCESSORS(csselr_el1)
 SYSREG_GEN_ACCESSORS(ccsidr_el1)
 SYSREG_GEN_ACCESSORS(ccsidr2_el1)
 SYSREG_GEN_ACCESSORS(ctr_el0)
+SYSREG_GEN_ACCESSORS(midr_el1)
 SYSREG_GEN_ACCESSORS(mpidr_el1)
 SYSREG_GEN_ACCESSORS(vmpidr_el2)
 SYSREG_GEN_ACCESSORS(cntvoff_el2)

src/arch/armv8/arch.mk

@@ -11,6 +11,8 @@ arch_profile_dir:=$(cpu_arch_dir)/$(ARCH_PROFILE)
 include $(arch_profile_dir)/profile.mk
 src_dirs+=$(arch_profile_dir)
 
+src_dirs+=$(arch_profile_dir)/cpus
+
 arch_profile_sub_dir:=$(arch_profile_dir)/$(ARCH_SUB)
 src_dirs+=$(arch_profile_sub_dir)
 
@@ -20,3 +22,4 @@ arch-cflags+=-mgeneral-regs-only
 endif
 arch-asflags+=
 arch-ldflags+=
+

src/arch/armv8/armv8-a/cpus/core_impl.c

@@ -0,0 +1,8 @@
+/**
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) Bao Project and Contributors. All rights reserved.
+ */
+
+#include <arch/core_impl.h>
+
+void cpu_arch_core_impl_init(void) { }

src/arch/armv8/armv8-a/cpus/objects.mk

@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: Apache-2.0
+## Copyright (c) Bao Project and Contributors. All rights reserved.
+
+cpu-objs-y+=$(ARCH_PROFILE)/cpus/core_impl.o

src/arch/armv8/armv8-r/cpus/core_impl.c

@@ -0,0 +1,29 @@
+/**
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) Bao Project and Contributors. All rights reserved.
+ */
+
+#include <arch/sysregs.h>
+#include <arch/core_impl.h>
+
+#define ARMV8R_R52_PARTNUMBER 0xD13
+
+/* Weak references to CPU implementation init functions */
+extern void cortex_r52_impl_init(void) __attribute__((weak));
+
+void cpu_arch_core_impl_init(void)
+{
+    /* Read MIDR to identify core implementation */
+    unsigned long midr = sysreg_midr_el1_read();
+    uint32_t part_num = MIDR_EL1_PARTNUM(midr);
+
+    switch (part_num) {
+        case ARMV8R_R52_PARTNUMBER: /* Cortex-R52 */
+            if (cortex_r52_impl_init != NULL) {
+                cortex_r52_impl_init();
+            }
+            break;
+        default:
+            break;
+    }
+}

src/arch/armv8/armv8-r/cpus/cortex_r52.c

@@ -0,0 +1,53 @@
+/**
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) Bao Project and Contributors. All rights reserved.
+ */
+
+#include <arch/sysregs.h>
+#include <arch/fences.h>
+
+/* HACTLR: Enable EL1 access to IMP DEF registers */
+#define HACTLR_PERIPHPREGIONR        (1 << 8)
+#define HACTLR_QOSR                  (1 << 9)
+#define HACTLR_ERR                   (1 << 13)
+
+/* IMP_PERIPHREGIONR (LLPP) */
+#define PERIPHREGIONR_EL1_EL0_ENABLE (1 << 0)
+#define PERIPHREGIONR_EL2_ENABLE     (1 << 1)
+
+/* FLASHIFREGIONR */
+#define FLASHIFREGIONR_ENABLE        (1 << 0)
+
+void cortex_r52_impl_init(void);
+
+static void cortex_r52_enable_hactlr(void)
+{
+    unsigned long val = sysreg_hactlr_read();
+    val |= (HACTLR_PERIPHPREGIONR | HACTLR_QOSR | HACTLR_ERR);
+    sysreg_hactlr_write(val);
+}
+
+static void cortex_r52_enable_llpp(void)
+{
+    unsigned long val = sysreg_imp_periphregionr_read();
+    val |= (PERIPHREGIONR_EL2_ENABLE | PERIPHREGIONR_EL1_EL0_ENABLE);
+    sysreg_imp_periphregionr_write(val);
+}
+
+static void cortex_r52_enable_flash_region(void)
+{
+    unsigned long val = sysreg_flashifregionr_read();
+    val |= FLASHIFREGIONR_ENABLE;
+    sysreg_flashifregionr_write(val);
+}
+
+void cortex_r52_impl_init(void)
+{
+    cortex_r52_enable_hactlr();
+
+    cortex_r52_enable_llpp();
+
+    cortex_r52_enable_flash_region();
+
+    ISB();
+}

src/arch/armv8/armv8-r/cpus/objects.mk

@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: Apache-2.0
+## Copyright (c) Bao Project and Contributors. All rights reserved.
+
+cpu-objs-y+=$(ARCH_PROFILE)/cpus/core_impl.o
+
+# CPU-specific implementations based on platform configuration
+cpu-objs-y+=$(foreach cpu, $(PLAT_CPUS), $(ARCH_PROFILE)/cpus/$(cpu).o)

src/arch/armv8/cpu.c

@@ -7,6 +7,7 @@
 #include <cpu.h>
 #include <platform.h>
 #include <arch/sysregs.h>
+#include <arch/core_impl.h>
 
 cpuid_t CPU_MASTER __attribute__((section(".datanocopy")));
 
@@ -15,6 +16,7 @@ void cpu_arch_init(cpuid_t cpuid, paddr_t load_addr)
 {
     cpu()->arch.mpidr = sysreg_mpidr_el1_read();
     cpu_arch_profile_init(cpuid, load_addr);
+    cpu_arch_core_impl_init();
 }
 
 unsigned long cpu_id_to_mpidr(cpuid_t id)