add support for hardening user_project_wrapper

[proppy]

Currently we CI seems to only harden the user project macro, it would be nice to also harden the user_project_wrapper so that we can also catch regression over the integration with caravel.

[proppy]

/cc @mithro @tspyrou

[maliberty]

Also the effective area is smaller. Anton had to remove the FPU from microwatt to make it fit.

[tspyrou]

@vijayank88 and @vvbandeira would it be hard to enhance this to also do what @proppy asks?

[vijayank88]

30% designs already added and running for user_project_wrapper.
Most of designs fails with DRC or LVS for wrapper designs. https://jenkins.openroad.tools/blue/organizations/jenkins/OpenLane-MPW-CI-Public%2Funstable-small-1/detail/PR-109/1/pipeline

Those who forked from efabless/caravel_user_project we're not able file github issue about design failures.

@dralabeing and @vvbandeira working on collecting user email ID to send automatic notification for design failures, so user can fix and update the repo.

[vijayank88]

@tspyrou @proppy
With existing user_project_wrapper itself we can able to figure out OpenLane flow/scripts/PDK issues, able to find and reporting back for the fixes. Do you want still to add all remaining user_project_wrapper shuttle designs in CI?

CI failures and respective issue reported with label MPW CI https://github.com/The-OpenROAD-Project/OpenLane/issues?q=label%3A%22MPW+CI%22+is%3Aclosed

[proppy]

30% designs already added and running for user_project_wrapper.

Can you give an example of such a design?

If I'm looking at a project like:

OpenLane-MPW-CI/scripts/spectrometer_hyperspace_mpw7/config.tcl

Line 7 in ae47acf

source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl

It seems that it only harden the wrapper and so will most likely reuse the pre-built macro check-in in the repo (which would be tied to sky130).

Do we have a mechanism to run the flow 2x per design?

• 1x for the user macro
• 1x for the user_project_wrapper

[proppy]

we can able to figure out OpenLane flow/scripts/PDK issues, able to find and reporting back for the fixes

For now, I'm mostly after getting some coverage on the number of design that can be ported with little to no change to PDK=gf180mcuC, but after we got "some designs" to pass the GF flow I do agree that it will be nice to file issue as regression if we find out a given tool commit make them fail.

[vijayank88]

@proppy
Here's list of user_project_wrapper design for sky130 pdk

./alu_xor_wrapper/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./axi_dma_wrapper/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./azadi_soc/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./caravel_soc_now/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./eFPGA_v3_wrapper/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./FMAC_wrapper/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./Ghazi_DFT/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./GPS_Baseband_wrapper/setup-flow.sh:sed -i '/::env(GLB_RT_MAXLAYER)/d' ${design_dir}/openlane/user_project_wrapper/config.tcl
./hack_soc_wrapper/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./keyvalue_caravel/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./ks-guitar-2s/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./mpw5_open_eFPGA/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./mpw7_AI_chip/setup-flow.sh:sed -i '/::env(RT_MAX_LAYER)/d' ${design_dir}/openlane/user_project_wrapper/config.tcl
./mpw7_open_eFPGA/config.tcl:                         $::env(DESIGN_DIR)/verilog/rtl/user_project_wrapper.v]
./NAND_Flash5/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./OpenFASOC_puplpino/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./openram_openmpw/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./patmos_chip/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./qf_wrapper/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./radiation_harden/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./rioschip/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./rioschip/setup-flow.sh:sed -i 's/SYNTH_TOP_LEVEL/SYNTH_ELABORATE_ONLY/g' ${design_dir}/openlane/user_project_wrapper/config.tcl
./riscduino_hikaysici/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./riscduino_wrapper/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./rocket_alpha/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./secure-memory-wrapper/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./SHA1_engine/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./spectrometer_hyperspace/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./spectrometer_hyperspace_mpw7/setup-flow.sh:sed -i 's/GLB_RT/GRT/g' ${design_dir}/openlane/user_project_wrapper/config.tcl
./sram_test/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./subservient_SOC/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./sudoku-accelerator/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./treepram/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./UETRV_wrapper/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./vsdbabysoc_wrapper/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./vsdmemsoc/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./wb_openram/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./yifive_r0/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./yonga-100m-ethernet/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./yonga_modbus_controller/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./yonga-serv-accelerator/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl
./zero_to_asic_mpw6/config.tcl:source $::env(DESIGN_DIR)/openlane/user_project_wrapper/config.tcl

[proppy]

Here's list of user_project_wrapper design for sky130 pdk

Yes, but it seems to me (if I'm reading the run_design.sh script correctly, that it would only harden the wrapper for those project (and not the actual project macro)

[vijayank88]

Yes, you're right. Its look for openlane/design_to_harden/config.tcl and run OpenLane flow for the same like caravel_user_project.
If design fails at any stage, respective changes applied through scripts/design_name/setup_flow.sh to complete the flow.

[proppy]

run OpenLane flow for the same like caravel_user_project.

yep, but as point in https://caravel-user-project.readthedocs.io/en/latest/#quickstart, caravel_user_project requires to run:

make user_proj_example
make user_project_wrapper

to go thru the whole flow.

So I believe we miss an extra make call for those project here:
https://github.com/The-OpenROAD-Project/OpenLane-MPW-CI/blob/main/scripts/run-design.sh#L55

[vijayank88]

@proppy
This CI setup made to pass some additional configuration through run_design.sh as not all designs works 100% at our end.
There are many configuration update from MPW-1 to MPW-7. So we made this way.
@vvbandeira you want to add any additional information on this?

[proppy]

This CI setup made to pass some additional configuration through run_design.sh as not all designs works 100% at our end.

I'm not really worried about setup_flow.sh , I think maintaining a layer of patches is a fine thing to do from the point of view of the CI (as long as you also try to submit them back to project for integration, or use it as a hint to document or fix backward compatibility issues in the tooling).

To be more precise: what I'm worried here is that, apparently for those projects:

• run_design.sh only runs flow.tcl on user_project_wrapper
• run_design.sh doesn't re-runs flow.tcl on the main user-provided project configuration to create the main user-provided project macro, and just end up reusing whatever is in the gds/ directory of the project submodules.

Maybe @QuantamHD or @mithro could jump in to try to clarify what I'm trying to express here.

[dralabeing]

@maliberty Can you elaborate on the issue faced by Anton? Was he unable to fit FPU on microwatt on a later shuttle that had updates to Caravel (user area)? Why is this a CI issue?

[maliberty]

It isn't a CI issue. It is case where you can't just use a skywater design unmodified on gf180. It is an effective area limitation.