OpenVADL floating point language features

[AndreasKrall]

I want to discuss the language features to specify floating point operations.
The beginning is an unordered list of requirements:

• both IEEE standard and non standard floating point formats and operations like fp8 have to be supported
• different rounding formats have to be supported
• raising of exceptions has to be supported
• subnormal numbers have to be supported
• probably both predefined and custom defined floating point types and formats have to be defined
• common information necessary like status register flags or exception raising for all instructions should be specified centrally and not distributed

Some resources:

• Wikipedia: Floating Point Arithmetic
• Wikipedia: IEEE 754
• What Every Computer Scientist Should Know About Floating- Point Arithmetic
• Efficient RISC-V-on-x64 Floating Point Simulation
• The RISC-V Instruction Set Manual: Volume I

For a well founded discussion I suggest to first do a simple implementation and afterwards start the discussion. The simple prototype implementation will cover

• two predefined floating point types FP32 and FP64 for IEEE 754 32 and 64 bit floating point types
• the only supported rounding mode is round to nearest - ties to even
• the following exception flags are supported
• NV invalid operation
• DZ divide by zero
• OF overflow
• UF underflow
• NX inexact
• some annotations to a register where it is specified which field maps to a floating point exception flag
• specification of quiet and signaling NaN
• all builtins and operators necessary to implement all RISC-V F and D instructions

The first draft implements the parser, type checking and QEMU iss generation.