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feat(river_hdl): adding microcode execution
1 parent d857916 commit 5a3330e

7 files changed

Lines changed: 994 additions & 593 deletions

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packages/riscv/lib/src/ops.dart

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1385,7 +1385,8 @@ class Microcode {
13851385
fieldIndices,
13861386
).width;
13871387

1388-
int get opIndexWidth => decodeLookup.keys.fold(0, (a, b) => a > b ? a : b);
1388+
int get opIndexWidth =>
1389+
decodeLookup.keys.fold(0, (a, b) => a > b ? a : b).bitLength;
13891390

13901391
int opWidth(Mxlen mxlen) => map.values
13911392
.map((op) => op.microcodeWidth(mxlen))

packages/river_hdl/lib/src/core.dart

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -245,7 +245,7 @@ class RiverCoreIP extends BridgeModule {
245245
// TODO: drive pagingMode, pageTableAddress, mxr, and sum from CSRs
246246
}
247247

248-
final microcodeRead = DataPortInterface(
248+
final microcodeDecodeRead = DataPortInterface(
249249
config.microcode.patternWidth,
250250
config.microcode.map.length.bitLength,
251251
);
@@ -255,7 +255,7 @@ class RiverCoreIP extends BridgeModule {
255255
clk,
256256
reset,
257257
[],
258-
[microcodeRead],
258+
[microcodeDecodeRead],
259259
numEntries: config.microcode.map.length,
260260
resetValue: config.microcode.encodedPatterns,
261261
definitionName: 'RiverMicrocodeLookup',
@@ -279,10 +279,13 @@ class RiverCoreIP extends BridgeModule {
279279
rs2Read,
280280
rdWrite,
281281
config.microcodeMode.onDecoder != MicrocodePipelineMode.none
282-
? microcodeRead
282+
? microcodeDecodeRead
283283
: null,
284+
null,
284285
useMixedDecoders:
285286
config.microcodeMode.onDecoder == MicrocodePipelineMode.in_parallel,
287+
useMixedExecution:
288+
config.microcodeMode.onExec == MicrocodePipelineMode.in_parallel,
286289
microcode: config.microcode,
287290
mxlen: config.mxlen,
288291
hasSupervisor: config.hasSupervisor,

packages/river_hdl/lib/src/core/csr.dart

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,7 @@ class RiscVCsrFile extends Module {
119119
addOutput('mideleg', width: mxlen.size);
120120
addOutput('medeleg', width: mxlen.size);
121121
addOutput('mtvec', width: mxlen.size);
122-
addOutput('stvec', width: mxlen.size);
122+
if (hasSupervisor) addOutput('stvec', width: mxlen.size);
123123

124124
void _checkFits(String n, int v) {
125125
final max = (mxlen.size >= 63) ? null : (1 << mxlen.size);
@@ -197,6 +197,7 @@ class RiscVCsrFile extends Module {
197197
_csrTop.getBackdoorPortsByAddr(0, CsrAddress.medeleg.address).rdData!;
198198
mtvec <=
199199
_csrTop.getBackdoorPortsByAddr(0, CsrAddress.mtvec.address).rdData!;
200+
200201
if (hasSupervisor)
201202
stvec! <=
202203
_csrTop.getBackdoorPortsByAddr(0, CsrAddress.stvec.address).rdData!;
@@ -568,17 +569,17 @@ class RiscVCsrFile extends Module {
568569
_fdRead.addr <= rdAddr12;
569570
_fdRead.en <= csrRead.en & rdLegal;
570571
csrRead.data <= _fdRead.data;
571-
csrRead.done <= _fdRead.done | csrRead.en;
572-
csrRead.valid <= _fdRead.valid & rdLegal;
572+
csrRead.done <= _fdRead.done & csrRead.en;
573+
csrRead.valid <= _fdRead.valid & csrRead.en & rdLegal;
573574

574575
_fdWrite.addr <= wrAddr12;
575576

576577
final maskedWriteData = _maskWriteData(wrAddr12, csrWrite.data);
577578
_fdWrite.data <= maskedWriteData;
578579

579580
_fdWrite.en <= csrWrite.en;
580-
csrWrite.done <= _fdWrite.done;
581-
csrWrite.valid <= _fdWrite.valid & wrLegal;
581+
csrWrite.done <= _fdWrite.done & csrWrite.en;
582+
csrWrite.valid <= _fdWrite.valid & csrWrite.en & wrLegal;
582583
}
583584

584585
void _bindBackdoorForCounters() {

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