Bootloader_spi

[Riufret]

I have an issue with the code generated by Harmony for the bootloader SPI.
I am experiencing data loss in the flash memory after a programming command.

In the "bootloader_spi.c" file, I noticed that when I modify the "spiBLData" struct to use "CACHE_ALIGN," it appears to resolve the problem.
static SPI_BL_DATA CACHE_ALIGN spiBLData;

During the execution of the "NVM_RowWrite()" function, it seems that the data must reside in a non-cache memory.
NVM_RowWrite((uint32_t*)&spiBLData.cmd.programCommand.data[spiBLData.dataBufferAlignOffset + spiBLData.nFlashBytesWritten], (spiBLData.cmd.programCommand.memAddr + spiBLData.nFlashBytesWritten));

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PIC32MZ2048EFM100
operating_system: Windows 10
mcc_mode: IDE # [IDE|Standalone|Headless]
mcc_version: v5.3.7
mcc_core_version: v5.5.7
mplabx_version: v6.05 # if MPLAB X plugin only
harmony_version: v1.3.2
compiler: XC32 (v4.30)

modules:
- {name: "csp", version: "v3.17.0"}
- {name: "core", version: "v3.13.0"}
- {name: "dev_packs", version: "v3.17.0"}
- {name: "bootloader", version: "v3.6.0"}

[vishalnxt]

@Riufret , thanks for reporting the issue. Yes, the NVM peripheral on PIC32MZ devices reads the data from SRAM buffer and programs it into the flash. Marking the buffer as cache aligned ensures that the buffer is allocated in physical memory and not cache. This is needed since NVM peripheral unlike CPU does not have access to the cache memory. Hence the data written to a buffer in cache by CPU may not be seen by the NVM peripheral. I will create an internal ticket to get this fixed.