dsim_project.dpf

---
# Note: The contents of this file are automatically generated.
# Any changes made by hand may be overwritten.
version: '0.2'
work_dir: .
design_root_dir: .
simulations:
  - name: build
    options: '-top work.tb -uvm 1.2 -genimage tb'
  - name: run
    options: >-
      -uvm 1.2 -image tb +UVM_TESTNAME=mem_test +acc+b -waves
      waves.mxd
  - name: build_and_run
    options: >-
      -top work.tb -uvm 1.2 +UVM_TESTNAME=mem_test +acc+b -waves
      waves.mxd
source_files:
  - language: verilog
    path: DUT/memory.sv
  - language: verilog
    path: Agent/mem_agent_pkg.sv
    options: '-uvm 1.2 +incdir+Agent'
  - language: verilog
    path: Agent/mem_if.sv
  - language: verilog
    path: Env/mem_env_pkg.sv
    options: '-uvm 1.2 +incdir+Env'
  - language: verilog
    path: Seq/mem_sequence_lib_pkg.sv
    options: '-uvm 1.2 +incdir+Seq'
  - language: verilog
    path: Test/mem_test_lib_pkg.sv
    options: '-uvm 1.2 +incdir+Test'
  - language: verilog
    path: TB/tb.sv
    options: '-uvm 1.2'
library_search_paths: []